This invention relates generally to wireless communication systems.
Wireless communication has extensive applications in consumer and business markets. Among the many communication applications/systems are: mobile wireless, fixed wireless, unlicensed Federal Communications Commission (FCC) wireless, local area network (LAN), cordless telephony, personal base station, telemetry, and others. The applications/systems are not limited to spread spectrum systems.
Signal processing protocols and standards have proliferated with advances in wireless communications devices and services. Current communications protocols include Frequency Division Multiplexing (FDM), Time Division Multiple Access (TDMA), and Code Division Multiple Access (CDMA). The United States, Europe, Japan, and Korea have all developed their own standards for each communications protocol. TDMA standards include interim Standard-136 (IS-136), Global System for Mobile (GSM), and General Packet Radio Service (GPRS). CDMA standards include Global Positioning System (GPS), Interim Standard-95 (IS-95) and Wide Band CDMA (WCDMA). Wireless communications services include paging, voice and data applications.
In many cases, within the same field of applications, different systems use incompatible modulation techniques and protocols. Consequently, each system may require unique hardware, software, and methodologies for baseband processing. This practice can be costly in terms of design, testing, manufacturing, and infrastructure resources. As a result, a need arises to overcome the limitations associated with the varied hardware, software, and methodology of processing digital signals in each of the varied applications.
Until recently wireless communications devices supported a single communications standard. In theory, however, a wireless communications device can be designed using a general purpose Digital Signal Processor (DSP) that would be programmed first to realize a set of functional blocks specifying the minimum performance requirements for a first application and can be reprogrammed to realize a second set of functional blocks to provide a second application. To achieve these minimum performance requirements, system designers design algorithms (sequences of arithmetic, trigonometric, logic, control, memory access, indexing operations, and the like) to encode, transmit, and decode signals. These algorithms are typically specified in software. The set of algorithms which achieve the target performance specification is collectively referred to as the executable specification. This executable specification can then be compiled and run on the DSP, typically via the use of a compiler. Despite the increasing computational power and speeds of general purpose DSPs and decreasing memory cost and size, designers have not been able to satisfy cost, power, and speed requirements simply by programming a general purpose DSP with the executable specification for a standard-specific application.
Additional dedicated high-speed processing is required, a need which has traditionally been met using an application-specific processor. As used herein, an application-specific processor is a processor that excels in the efficient execution (power, area, flexibility) of a set of algorithms tailored to the application. An application-specific processor, however, fares extremely poorly for algorithms outside the intended application space. In other words, the improved speed and power efficiency of application-specific-processors comes at the cost of function flexibility.
Demand is now growing for wireless communications devices that support multiple applications and varying grades of services over multiple standards. Today's solution to this problem is essentially to connect multiple application-specific processors together to obtain multi-standard operation, thereby adding cost in terms of design resources, design time, and silicon area. In particular, demand is growing for cellular handsets, which is one type of wireless communications device, to support multiple applications and services over multiple standards.
Cellular handsets, including PCS (Personal Communications Services) and 3-G (Third Generation) handsets, need to acquire certain cell specific information and characteristics before negotiating a service with a base station. For this purpose, each base station transmits certain cell specific information (e.g., a pilot signal) necessary for a user to acquire services such as paging or cellular telephony from the base station. For example, in CDMA systems, the cell specific information is contained in pilot and/or synchronization channels. The pilot and/or synchronization channels are spread with cell specific pseudo-random or gold code sequences, which form the basis for frame, slot, and bit timing synchronization for a handset.
To acquire cellular service, a cellular handset must be capable of searching for a base station. Typically, a handset performs two types of searches, namely, access search and directed search. The access search is generally performed at power-up, where the handset searches for the pilot signal to identify the base station in the geographic area. During an access search, the search area is limited by the maximum distance associated with a base station radius. Once a base station is identified, the handset periodically performs directed searches to establish multi-path updates. During a directed search, the general location of the base station is known; thus, the directed search is conducted within a hypothesis area, which is smaller than the access search area.
In similar fashion, a base station searches for the handsets in its service area.
As might be expected, it is desirable to reduce search time for a cellular handset to acquire service. Dwell state algorithms are methods to reduce search time. In a typical dwell state algorithm, a search is binned according to energy values or thresholds. An auto-correlation function at a given integration length is performed for all energy values that are high enough to be distinguished from the noise floor with a high degree of accuracy. As the search progresses, the integration length and the threshold value generally progresses to a higher value. Typically, the longer the integration length, the more reliable the result but the longer the search time. Thus, it is desirable to reduce search time yet still provide reliable search results.
One of the primary concerns when designing a searcher to perform search functions is to achieve an optimal balance between configuration flexibility and performance level. Typically, a searcher having very high configuration flexibility, such as a DSP, yields low performance throughput. In time-sliced architecture, a search engine is typically running at a clock speed much greater than chip rate of the logical device; thus, a higher performance is desired to quickly update state machine implementations of dwell states. A searcher implemented on an application specific integrated circuit (ASIC) is typically able to yield high performance throughput. ASIC searchers, however, generally have very limited or no configuration flexibility.
Accordingly, it is desirable to provide a multi-dwell search engine that provides a sufficient amount of configuration flexibility yet yielding a high performance throughput. It is further desirable to provide a multi-dwell search engine that reduces search time while providing reliable search results.